高通8953平台SN65DSI84调试

4 CHA_COR_ECC_ERR R/W 0 When the DSI channel A packet processor detects a correctable
ECC error, this bit is set; this bit is cleared by writing a ‘1’ value.
3 CHA_LLP_ERR R/W 0 When the DSI channel A packet processor detects a low level
protocol error, this bit is set; this bit is cleared by writing a ‘1’
value.
Low level protocol errors include SoT and EoT sync errors,
Escape Mode entry command errors, LP transmission sync
errors, and false control errors. Lane merge errors are reported
by this status condition.
2 CHA_SOT_BIT_ERR R/W 0 When the DSI channel A packet processor detects an SoT
leader sequence bit error, this bit is set; this bit is cleared by
writing a ‘1’ value.

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