
ADS6442: 采集正弦波有乱码
Part Number:ADS6442Other Parts Discussed in Thread:THS4552, 采用ADS6442采集四路正弦波,采样率10MHz。四路频率100KHz幅度1Vpp的单端正弦波通过两片THS4552转...

Part Number:ADS6442Other Parts Discussed in Thread:THS4552, 采用ADS6442采集四路正弦波,采样率10MHz。四路频率100KHz幅度1Vpp的单端正弦波通过两片THS4552转...

我使用FPGA对ads6442进行控制采样,使用2-WIRE INTERFACE – 16× SERIALIZATION WITH DDR In Byte-wise mode 模式用9.6MHz对一个50KHZ,幅度...

我使用FPGA对ads6442进行控制采样,使用2-WIRE INTERFACE – 16× SERIALIZATION WITH DDR In Byte-wise mode 模式用9.6MHz对一个50KHZ,幅度...
用altera cyclone III FPGA产生一对8M的采集差分时钟给ADS6442,并行配置,经过测试并行配置没有差错,但DCLK,FCLK输出有问题,在signaltap ii 上观察dclk,fclk是杂乱无章的时钟信号,根据逻...
我在设计中用到贵公司A/D芯片ADS6442芯片,我做了一个试验,在ADS6442输入端加单频正弦波信号,分别加500K,1M,2M,15M,30M,70.5M,80.5M的正弦波,幅度为1Vpp左右,然后我采样时钟频率为62M的LVPEC...