dac_DELAY 的这个样例的问题

interrupt void adca1_isr(void)
{
//DLYSTAMP will read 2 if the sample was not delayed
if(2 < AdcaRegs.ADCPPB1STAMP.bit.DLYSTAMP){
//if DLYSTAMP > 2, then the sample was delayed by (DLYSTAMP – 2) cycles (SYSCLK)
conversion[delay_index] = conversion_count;
delay[delay_index] = AdcaRegs.ADCPPB1STAMP.bit.DLYSTAMP – 2; //save sample delay
delay_index++;

//corrective action(s) for delayed sample can occur here
//…
}

为什么设定当采样没有延时，读DLYSTAMP为2，如果 DLYSTAMP > 2, 采样延时了 (DLYSTAMP – 2)个周期 ？？

Jason Wu4：

这个是DAC系统模块的设计设定，用户只用参照使用即可