TI中文支持网这个是28377死区的例程
#include "F28x_Project.h"
//
// Defines
//
#define EPWM1_MAX_DB 0x03FF
#define EPWM2_MAX_DB 0x03FF
#define EPWM3_MAX_DB 0x03FF
#define EPWM1_MIN_DB 0
#define EPWM2_MIN_DB 0
#define EPWM3_MIN_DB 0
#define DB_UP 1
#define DB_DOWN 0
//
// Globals
//
Uint32 EPwm1TimerIntCount;
Uint32 EPwm2TimerIntCount;
Uint32 EPwm3TimerIntCount;
Uint16 EPwm1_DB_Direction;
Uint16 EPwm2_DB_Direction;
Uint16 EPwm3_DB_Direction;
Uint16 RR=0,temp10=0;
//
// Function Prototypes
//
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
__interrupt void epwm1_isr(void);
__interrupt void epwm2_isr(void);
__interrupt void epwm3_isr(void);
//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
InitSysCtrl();
//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to its default state.
//
// InitGpio();
//
// enable PWM1, PWM2 and PWM3
//
CpuSysRegs.PCLKCR2.bit.EPWM1=1;
CpuSysRegs.PCLKCR2.bit.EPWM2=1;
CpuSysRegs.PCLKCR2.bit.EPWM3=1;
//
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F2837xD_EPwm.c file
//
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
InitPieVectTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &epwm1_isr;
PieVectTable.EPWM2_INT = &epwm2_isr;
PieVectTable.EPWM3_INT = &epwm3_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
//
// Step 4. Initialize the Device Peripherals:
//
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EDIS;
//
// Step 5. User specific code, enable interrupts:
// Initialize counters:
//
EPwm1TimerIntCount = 0;
EPwm2TimerIntCount = 0;
EPwm3TimerIntCount = 0;
//
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
IER |= M_INT3;
//
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
//
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
//
// Enable global Interrupts and higher priority real-time debug events:
//
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//
// Step 6. IDLE loop. Just sit and loop forever (optional):
//
for(;;)
{
asm (" NOP");
}
}
//
// epwm1_isr – EPWM1 ISR
//
__interrupt void epwm1_isr(void)
{
if(EPwm1_DB_Direction == DB_UP)
{
if(EPwm1Regs.DBFED.bit.DBFED < EPWM1_MAX_DB)
{
EPwm1Regs.DBFED.bit.DBFED++;
EPwm1Regs.DBRED.bit.DBRED++;
}
else
{
EPwm1_DB_Direction = DB_DOWN;
EPwm1Regs.DBFED.bit.DBFED–;
EPwm1Regs.DBRED.bit.DBRED–;
}
}
else
{
if(EPwm1Regs.DBFED.bit.DBFED == EPWM1_MIN_DB)
{
EPwm1_DB_Direction = DB_UP;
EPwm1Regs.DBFED.bit.DBFED++;
EPwm1Regs.DBRED.bit.DBRED++;
}
else
{
EPwm1Regs.DBFED.bit.DBFED–;
EPwm1Regs.DBRED.bit.DBRED–;
}
}
EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
//
// Acknowledge this interrupt to receive more interrupts from group 3
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//EPwm1Regs.CMPA.bit.CMPA =temp10;
// Clear INT flag for this timer
//
}
//
// epwm2_isr – EPWM2 ISR
//
__interrupt void epwm2_isr(void)
{
if(EPwm2_DB_Direction == DB_UP)
{
if(EPwm2Regs.DBFED.bit.DBFED < EPWM2_MAX_DB)
{
EPwm2Regs.DBFED.bit.DBFED++;
EPwm2Regs.DBRED.bit.DBRED++;
}
else
{
EPwm2_DB_Direction = DB_DOWN;
EPwm2Regs.DBFED.bit.DBFED–;
EPwm2Regs.DBRED.bit.DBRED–;
}
}
else
{
if(EPwm2Regs.DBFED.bit.DBFED == EPWM2_MIN_DB)
{
EPwm2_DB_Direction = DB_UP;
EPwm2Regs.DBFED.bit.DBFED++;
EPwm2Regs.DBRED.bit.DBRED++;
}
else
{
EPwm2Regs.DBFED.bit.DBFED–;
EPwm2Regs.DBRED.bit.DBRED–;
}
}
EPwm2TimerIntCount++;
//
// Clear INT flag for this timer
//
EPwm2Regs.ETCLR.bit.INT = 1;
//
// Acknowledge this interrupt to receive more interrupts from group 3
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
//
// epwm3_isr – EPWM3 ISR
//
__interrupt void epwm3_isr(void)
{
if(EPwm3_DB_Direction == DB_UP)
{
if(EPwm3Regs.DBFED.bit.DBFED < EPWM3_MAX_DB)
{
EPwm3Regs.DBFED.bit.DBFED++;
EPwm3Regs.DBRED.bit.DBRED++;
}
else
{
EPwm3_DB_Direction = DB_DOWN;
EPwm3Regs.DBFED.bit.DBFED–;
EPwm3Regs.DBRED.bit.DBRED–;
}
}
else
{
if(EPwm3Regs.DBFED.bit.DBFED == EPWM3_MIN_DB)
{
EPwm3_DB_Direction = DB_UP;
EPwm3Regs.DBFED.bit.DBFED++;
EPwm3Regs.DBRED.bit.DBRED++;
}
else
{
EPwm3Regs.DBFED.bit.DBFED–;
EPwm3Regs.DBRED.bit.DBRED–;
}
}
EPwm3TimerIntCount++;
//
// Clear INT flag for this timer
//
EPwm3Regs.ETCLR.bit.INT = 1;
//
// Acknowledge this interrupt to receive more interrupts from group 3
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
//
// InitEPwm1Example – Initialize EPWM1 configuration
//
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 6000; // Set timer period
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm1Regs.CMPA.bit.CMPA = 3000;
//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;
//
// Active Low PWMs – Setup Deadband
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED.bit.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED.bit.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;
//
// Interrupt where we will change the Deadband
//
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//
// InitEPwm2Example – Initialize EPWM2 configuration
//
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 6000; // Set timer period
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow just to observe on
// the scope
//
// Setup compare
//
EPwm2Regs.CMPA.bit.CMPA = 3000;
//
// Set actions
//
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
EPwm2Regs.AQCTLB.bit.CAD = AQ_SET;
//
// Active Low complementary PWMs – setup the deadband
//
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED.bit.DBRED = EPWM2_MIN_DB;
EPwm2Regs.DBFED.bit.DBFED = EPWM2_MIN_DB;
EPwm2_DB_Direction = DB_UP;
//
// Interrupt where we will modify the deadband
//
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//
// InitEPwm3Example – Initialize EPWM3 configuration
//
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 6000; // Set timer period
EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow so we can observe on
// the scope
//
// Setup compare
//
EPwm3Regs.CMPA.bit.CMPA = 3000;
//
// Set actions
//
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on Zero
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
//
// Active high complementary PWMs – Setup the deadband
//
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED.bit.DBRED = EPWM3_MIN_DB;
EPwm3Regs.DBFED.bit.DBFED = EPWM3_MIN_DB;
EPwm3_DB_Direction = DB_UP;
//
// Interrupt where we will change the deadband
//
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//
// End of file
//
在EPwm3TimerIntCount++;后边加了
if(RR>=20)
{ RR=1;}
else
{ RR=RR+1;}
if(RR<=3)
//if(n==10)
temp10=temp10+400;
else {temp10 =0;}
if (EPwm1Regs.CMPCTL.bit.SHDWAFULL==0)
{
EPwm1Regs.CMPA.bit.CMPA =temp10;
}
搞不懂出来脉冲为什么会是9个，分析应该是3个
Green Deng：抱歉程序实在有点长，没过多关注。
你说的脉冲是9个而不是3个，具体是指什么脉冲？PWM输出脉冲？最好附上图片介绍一下这样更直观点。
这个是28377死区的例程
#include "F28x_Project.h"
//
// Defines
//
#define EPWM1_MAX_DB 0x03FF
#define EPWM2_MAX_DB 0x03FF
#define EPWM3_MAX_DB 0x03FF
#define EPWM1_MIN_DB 0
#define EPWM2_MIN_DB 0
#define EPWM3_MIN_DB 0
#define DB_UP 1
#define DB_DOWN 0
//
// Globals
//
Uint32 EPwm1TimerIntCount;
Uint32 EPwm2TimerIntCount;
Uint32 EPwm3TimerIntCount;
Uint16 EPwm1_DB_Direction;
Uint16 EPwm2_DB_Direction;
Uint16 EPwm3_DB_Direction;
Uint16 RR=0,temp10=0;
//
// Function Prototypes
//
void InitEPwm1Example(void);
void InitEPwm2Example(void);
void InitEPwm3Example(void);
__interrupt void epwm1_isr(void);
__interrupt void epwm2_isr(void);
__interrupt void epwm3_isr(void);
//
// Main
//
void main(void)
{
//
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the F2837xD_SysCtrl.c file.
//
InitSysCtrl();
//
// Step 2. Initialize GPIO:
// This example function is found in the F2837xD_Gpio.c file and
// illustrates how to set the GPIO to its default state.
//
// InitGpio();
//
// enable PWM1, PWM2 and PWM3
//
CpuSysRegs.PCLKCR2.bit.EPWM1=1;
CpuSysRegs.PCLKCR2.bit.EPWM2=1;
CpuSysRegs.PCLKCR2.bit.EPWM3=1;
//
// For this case just init GPIO pins for ePWM1, ePWM2, ePWM3
// These functions are in the F2837xD_EPwm.c file
//
InitEPwm1Gpio();
InitEPwm2Gpio();
InitEPwm3Gpio();
//
// Step 3. Clear all interrupts and initialize PIE vector table:
// Disable CPU interrupts
//
DINT;
//
// Initialize the PIE control registers to their default state.
// The default state is all PIE interrupts disabled and flags
// are cleared.
// This function is found in the F2837xD_PieCtrl.c file.
//
InitPieCtrl();
//
// Disable CPU interrupts and clear all CPU interrupt flags:
//
IER = 0x0000;
IFR = 0x0000;
//
// Initialize the PIE vector table with pointers to the shell Interrupt
// Service Routines (ISR).
// This will populate the entire table, even if the interrupt
// is not used in this example. This is useful for debug purposes.
// The shell ISR routines are found in F2837xD_DefaultIsr.c.
// This function is found in F2837xD_PieVect.c.
//
InitPieVectTable();
//
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
//
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.EPWM1_INT = &epwm1_isr;
PieVectTable.EPWM2_INT = &epwm2_isr;
PieVectTable.EPWM3_INT = &epwm3_isr;
EDIS; // This is needed to disable write to EALLOW protected registers
//
// Step 4. Initialize the Device Peripherals:
//
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =0;
EDIS;
InitEPwm1Example();
InitEPwm2Example();
InitEPwm3Example();
EALLOW;
CpuSysRegs.PCLKCR0.bit.TBCLKSYNC =1;
EDIS;
//
// Step 5. User specific code, enable interrupts:
// Initialize counters:
//
EPwm1TimerIntCount = 0;
EPwm2TimerIntCount = 0;
EPwm3TimerIntCount = 0;
//
// Enable CPU INT3 which is connected to EPWM1-3 INT:
//
IER |= M_INT3;
//
// Enable EPWM INTn in the PIE: Group 3 interrupt 1-3
//
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
PieCtrlRegs.PIEIER3.bit.INTx2 = 1;
PieCtrlRegs.PIEIER3.bit.INTx3 = 1;
//
// Enable global Interrupts and higher priority real-time debug events:
//
EINT; // Enable Global interrupt INTM
ERTM; // Enable Global realtime interrupt DBGM
//
// Step 6. IDLE loop. Just sit and loop forever (optional):
//
for(;;)
{
asm (" NOP");
}
}
//
// epwm1_isr – EPWM1 ISR
//
__interrupt void epwm1_isr(void)
{
if(EPwm1_DB_Direction == DB_UP)
{
if(EPwm1Regs.DBFED.bit.DBFED < EPWM1_MAX_DB)
{
EPwm1Regs.DBFED.bit.DBFED++;
EPwm1Regs.DBRED.bit.DBRED++;
}
else
{
EPwm1_DB_Direction = DB_DOWN;
EPwm1Regs.DBFED.bit.DBFED–;
EPwm1Regs.DBRED.bit.DBRED–;
}
}
else
{
if(EPwm1Regs.DBFED.bit.DBFED == EPWM1_MIN_DB)
{
EPwm1_DB_Direction = DB_UP;
EPwm1Regs.DBFED.bit.DBFED++;
EPwm1Regs.DBRED.bit.DBRED++;
}
else
{
EPwm1Regs.DBFED.bit.DBFED–;
EPwm1Regs.DBRED.bit.DBRED–;
}
}
EPwm1TimerIntCount++;
EPwm1Regs.ETCLR.bit.INT = 1;
//
// Acknowledge this interrupt to receive more interrupts from group 3
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
//EPwm1Regs.CMPA.bit.CMPA =temp10;
// Clear INT flag for this timer
//
}
//
// epwm2_isr – EPWM2 ISR
//
__interrupt void epwm2_isr(void)
{
if(EPwm2_DB_Direction == DB_UP)
{
if(EPwm2Regs.DBFED.bit.DBFED < EPWM2_MAX_DB)
{
EPwm2Regs.DBFED.bit.DBFED++;
EPwm2Regs.DBRED.bit.DBRED++;
}
else
{
EPwm2_DB_Direction = DB_DOWN;
EPwm2Regs.DBFED.bit.DBFED–;
EPwm2Regs.DBRED.bit.DBRED–;
}
}
else
{
if(EPwm2Regs.DBFED.bit.DBFED == EPWM2_MIN_DB)
{
EPwm2_DB_Direction = DB_UP;
EPwm2Regs.DBFED.bit.DBFED++;
EPwm2Regs.DBRED.bit.DBRED++;
}
else
{
EPwm2Regs.DBFED.bit.DBFED–;
EPwm2Regs.DBRED.bit.DBRED–;
}
}
EPwm2TimerIntCount++;
//
// Clear INT flag for this timer
//
EPwm2Regs.ETCLR.bit.INT = 1;
//
// Acknowledge this interrupt to receive more interrupts from group 3
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
//
// epwm3_isr – EPWM3 ISR
//
__interrupt void epwm3_isr(void)
{
if(EPwm3_DB_Direction == DB_UP)
{
if(EPwm3Regs.DBFED.bit.DBFED < EPWM3_MAX_DB)
{
EPwm3Regs.DBFED.bit.DBFED++;
EPwm3Regs.DBRED.bit.DBRED++;
}
else
{
EPwm3_DB_Direction = DB_DOWN;
EPwm3Regs.DBFED.bit.DBFED–;
EPwm3Regs.DBRED.bit.DBRED–;
}
}
else
{
if(EPwm3Regs.DBFED.bit.DBFED == EPWM3_MIN_DB)
{
EPwm3_DB_Direction = DB_UP;
EPwm3Regs.DBFED.bit.DBFED++;
EPwm3Regs.DBRED.bit.DBRED++;
}
else
{
EPwm3Regs.DBFED.bit.DBFED–;
EPwm3Regs.DBRED.bit.DBRED–;
}
}
EPwm3TimerIntCount++;
//
// Clear INT flag for this timer
//
EPwm3Regs.ETCLR.bit.INT = 1;
//
// Acknowledge this interrupt to receive more interrupts from group 3
//
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
//
// InitEPwm1Example – Initialize EPWM1 configuration
//
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = 6000; // Set timer period
EPwm1Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm1Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;
EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW; // Load registers every ZERO
EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
//
// Setup compare
//
EPwm1Regs.CMPA.bit.CMPA = 3000;
//
// Set actions
//
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM1A on Zero
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM1A on Zero
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;
//
// Active Low PWMs – Setup Deadband
//
EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED.bit.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED.bit.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;
//
// Interrupt where we will change the Deadband
//
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//
// InitEPwm2Example – Initialize EPWM2 configuration
//
void InitEPwm2Example()
{
EPwm2Regs.TBPRD = 6000; // Set timer period
EPwm2Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm2Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm2Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm2Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm2Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm2Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow just to observe on
// the scope
//
// Setup compare
//
EPwm2Regs.CMPA.bit.CMPA = 3000;
//
// Set actions
//
EPwm2Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM2A on Zero
EPwm2Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm2Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM2A on Zero
EPwm2Regs.AQCTLB.bit.CAD = AQ_SET;
//
// Active Low complementary PWMs – setup the deadband
//
EPwm2Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm2Regs.DBCTL.bit.POLSEL = DB_ACTV_LOC;
EPwm2Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm2Regs.DBRED.bit.DBRED = EPWM2_MIN_DB;
EPwm2Regs.DBFED.bit.DBFED = EPWM2_MIN_DB;
EPwm2_DB_Direction = DB_UP;
//
// Interrupt where we will modify the deadband
//
EPwm2Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm2Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm2Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//
// InitEPwm3Example – Initialize EPWM3 configuration
//
void InitEPwm3Example()
{
EPwm3Regs.TBPRD = 6000; // Set timer period
EPwm3Regs.TBPHS.bit.TBPHS = 0x0000; // Phase is 0
EPwm3Regs.TBCTR = 0x0000; // Clear counter
//
// Setup TBCLK
//
EPwm3Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm3Regs.TBCTL.bit.PHSEN = TB_DISABLE; // Disable phase loading
EPwm3Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4; // Clock ratio to SYSCLKOUT
EPwm3Regs.TBCTL.bit.CLKDIV = TB_DIV4; // Slow so we can observe on
// the scope
//
// Setup compare
//
EPwm3Regs.CMPA.bit.CMPA = 3000;
//
// Set actions
//
EPwm3Regs.AQCTLA.bit.CAU = AQ_SET; // Set PWM3A on Zero
EPwm3Regs.AQCTLA.bit.CAD = AQ_CLEAR;
EPwm3Regs.AQCTLB.bit.CAU = AQ_CLEAR; // Set PWM3A on Zero
EPwm3Regs.AQCTLB.bit.CAD = AQ_SET;
//
// Active high complementary PWMs – Setup the deadband
//
EPwm3Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm3Regs.DBCTL.bit.POLSEL = DB_ACTV_HIC;
EPwm3Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm3Regs.DBRED.bit.DBRED = EPWM3_MIN_DB;
EPwm3Regs.DBFED.bit.DBFED = EPWM3_MIN_DB;
EPwm3_DB_Direction = DB_UP;
//
// Interrupt where we will change the deadband
//
EPwm3Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO; // Select INT on Zero event
EPwm3Regs.ETSEL.bit.INTEN = 1; // Enable INT
EPwm3Regs.ETPS.bit.INTPRD = ET_3RD; // Generate INT on 3rd event
}
//
// End of file
//
在EPwm3TimerIntCount++;后边加了
if(RR>=20)
{ RR=1;}
else
{ RR=RR+1;}
if(RR<=3)
//if(n==10)
temp10=temp10+400;
else {temp10 =0;}
if (EPwm1Regs.CMPCTL.bit.SHDWAFULL==0)
{
EPwm1Regs.CMPA.bit.CMPA =temp10;
}
搞不懂出来脉冲为什么会是9个，分析应该是3个
mangui zhang：没有寄存器的控制通过if判断控制比较值这种输出脉冲数不好控制
