想要DSP28035epwm1和epwm2时钟同步，请问寄存器怎么配置？

   这里我配置的寄存器，但是仍然有相位差？还有什么地方需要配置么？

// Setup TBCLK
   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4;       // Clock ratio to SYSCLKOUT
   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;

   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;

   // Setup TBCLK
   EPwm2Regs.TBCTL.bit.CTRMODE =2;     // Count up
   EPwm2Regs.TBCTL.bit.PHSEN = 0;    // Disable phase loading
   EPwm2Regs.TBCTL.bit.PRDLD = 0;
   EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;       // Clock ratio to SYSCLKOUT
   EPwm2Regs.TBCTL.bit.CLKDIV = 0;
   EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
  // EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
   EPwm2Regs.TBCTL.bit.SWFSYNC = 1;
   EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;

mangui zhang：能差多少啊我觉得小于3度正常吧

   这里我配置的寄存器，但是仍然有相位差？还有什么地方需要配置么？

// Setup TBCLK
   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4;       // Clock ratio to SYSCLKOUT
   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;

   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;

   // Setup TBCLK
   EPwm2Regs.TBCTL.bit.CTRMODE =2;     // Count up
   EPwm2Regs.TBCTL.bit.PHSEN = 0;    // Disable phase loading
   EPwm2Regs.TBCTL.bit.PRDLD = 0;
   EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;       // Clock ratio to SYSCLKOUT
   EPwm2Regs.TBCTL.bit.CLKDIV = 0;
   EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
  // EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
   EPwm2Regs.TBCTL.bit.SWFSYNC = 1;
   EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;

Seven Han：您参考写这边帖子：e2echina.ti.com/…/142347

   这里我配置的寄存器，但是仍然有相位差？还有什么地方需要配置么？

// Setup TBCLK
   EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
   EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;        // Disable phase loading
   EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4;       // Clock ratio to SYSCLKOUT
   EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;

   EPwm1Regs.CMPCTL.bit.SHDWAMODE = CC_SHADOW;    // Load registers every ZERO
   EPwm1Regs.CMPCTL.bit.SHDWBMODE = CC_SHADOW;
   EPwm1Regs.CMPCTL.bit.LOADAMODE = CC_CTR_ZERO;
   EPwm1Regs.CMPCTL.bit.LOADBMODE = CC_CTR_ZERO;
   EPwm1Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;

   // Setup TBCLK
   EPwm2Regs.TBCTL.bit.CTRMODE =2;     // Count up
   EPwm2Regs.TBCTL.bit.PHSEN = 0;    // Disable phase loading
   EPwm2Regs.TBCTL.bit.PRDLD = 0;
   EPwm2Regs.TBCTL.bit.HSPCLKDIV = 0;       // Clock ratio to SYSCLKOUT
   EPwm2Regs.TBCTL.bit.CLKDIV = 0;
   EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_SYNC_IN;
  // EPwm2Regs.TBCTL.bit.SYNCOSEL = TB_CTR_ZERO;
   EPwm2Regs.TBCTL.bit.SWFSYNC = 1;
   EPwm2Regs.TBCTL.bit.PRDLD = TB_SHADOW;

Young Hu：

回复 Seven Han:

您好，
ePWM User's Guide里面有很多个拓扑的例程，最好是参考例程来设计。