AM625: Questions Regarding Configuration of CP_GEMAC_CPTS0_RFT_CLK on AM6254A Using SDK 09.02.01.09

Dear TI Support Team,

I am currently working with the AM6254A processor and using SDK version09.02.01.09. For reference, the documentation I’m following is titled"AM62x Processors Silicon Revision 1.0 – Texas Instruments Families of Products."

I would like to configureCPTS_RFT_CLK sourced fromCP_GEMAC_CPTS0_RFT_CLK, and I have performed the following steps:

1. I configured the general-purpose register0x000F41F0 for theCP_GEMAC_CPTS0_RFT_CLK pin A18 with the value0x08254006, enabling the input function and setting the pin mux toCP_GEMAC_CPTS0_RFT_CLK.

2. Based on the requirements, I attempted to configure theCPTS_CLKSEL register to selectCP_GEMAC_CPTS0_RFT_CLK as the input source. I also intend to feed in a clock signal ranging from 125MHz to 650MHz (I have an external PLL capable of outputting a sine wave within this frequency range).

   

I now have the following questions and would appreciate your guidance:

1. Are the above configuration steps feasible and valid for setting upCP_GEMAC_CPTS0_RFT_CLK as the source forCPTS_RFT_CLK?

2. If I input a 125MHz signal toCP_GEMAC_CPTS0_RFT_CLK, what are the required electrical levels and waveform characteristics (e.g., voltage standard, duty cycle, waveform shape)?

3. I was unable to locate the following registers or fields in the documentation:

   • CPTS_CLKSEL

   • CPTS_EN

   • TS_PEND_EN

   • ADD_VAL[2-0]

   • TheMODE[5] bit which is mentioned in the phrase: “64-bit mode is selected when [5] MODE bit set to 1h”

   I did find references that may correspond to these:

   • CPTS_CLKSEL might beCPSW_CKJSEL

   • ADD_VAL[2-0] might correspond toCPSW_NUSS_VBUSP_CPSW_NU_CPTS_TS_ADD_VAL_REG

     

   However, I could not find clear documentation for the others. Could you please confirm their correct register names and locations?

4. I came across the following forum post, which discusses using device tree configuration for AM64x:

   TI E2E Forum Reference Post

   In that post,AM64X_DEV_CPSW0 has mapped clock IDs. How can I identify or trace similar clock mapping IDs for the AM6254A in the device tree or TI SDK?

5. Are there any existing reference implementations or sample configurations available for usingCP_GEMAC_CPTS0_RFT_CLK as the CPTS reference clock input?

Thank you in advance for your support and guidance.

Best regards,
TiAmo

Eirwen：

Hello!

We have received your case and the investigation will take some time. Thank you for your patience.

,

Eirwen：

Can you tell us a bit more about the usecase here? How are you planning to use the CPTS?

What OS is running on the A53 cores? I assume that you are planning on controlling the CPTS from the A53 cores.

,

qingsheng Yin：

I am working on synchronizing the CPTS (Common Platform Time Sync) with an external reference on our AM6254A board, which runs Linux kernel 6.1.80 on the Cortex‑A53.

Currently, I have fed a 125 MHz square‑wave signal into CP_GEMAC_CPTS0_RFT_CLK and configured the relevant registers to route this to the rclk source. The input clock is recognized correctly by the system.

However, I need detailed criteria for the external clock to ensure reliable and precise operation. Specifically, I would like guidance or documentation on the following signal parameters:

Frequency tolerance (in ppm or ppb)

Jitter requirements, including cycle‑to‑cycle, phase jitter, and TIE jitter

Rise/fall time specifications (clock edge constraints)

Output drive strength and load matching requirements

I have not located device-specific specifications for the external CP_GEMAC_CPTS0_RFT_CLK input.

Could you please point me to the datasheet or technical reference that defines these electrical requirements? Alternatively, are there any validated reference designs or hardware test cases for CPTS external clocking that meet TI’s recommended criteria?

Thank you for your assistance.

Best regards, TiAmo