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When SCI Transmit FIFO is empty, how long does the FIFO interrupt actives?

I'm using F28035,enable SCI Transmit FIFO interrupt (TXFFIENA=1), and set TXFFIL=0 (Transmit FIFO interrupt level bits). 

Some times when run into Transmit FIFO interrupt ISR, I get no data to write to the TX FIFO ( thus the TX FIFO is empty for a long time), and I find the ISR will active continuously (this mode works for me), but I do not know how long does the interrupts active between one from another?

Annie Liu:

您的问题在E2E英文论坛已有工程师跟进,请继续关注。http://e2e.ti.com/support/microcontrollers/c2000/f/171/t/788395?tisearch=e2e-sitesearch&keymatch=When%20SCI%20Transmit%20FIFO%20is%20empty

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