两片6455菊花链连接 560V2问题

两片6455菊花链连接，JTAG_TDI—–DSP1_TDI——-DSP1_TDO——-DSP2_TDI——DSP2_TDO——-JTAG_TDO,用560V2链接时，无法链接，测试TCK引脚时钟为500KHz,请帮忙分析一下是什么问题，谢谢了！

Allen35065：

首先需要确定6455是否正确上电，检查SYSCLKOUT是否有正确输出（首先使能SYSCLKOUT_EN）。

另请贴出560V2链接时的报错log

thomas liu1：

回复 Allen35065:

Dear Allen,

非常感谢你的帮忙!已经检查过6455上电正常，SYSCLKOUT输出正常，另贴CCS报错图片，Thank very much！

Allen35065：

回复 thomas liu1:

从你的描述来看，JTAG接的方式没有问题，DSP也正常启动了，需要确认几个问题，

1. 你们使用的JTAG型号是SD的LAN 560v2无误？

2. 最好是在target建立界面进行test connection， 能看到更多的log

3. JTAG链路是否驱动不够？

Forrest2：

回复 Allen35065:

您好，我也遇到了类似的问题，我用560v2连接两片菊花链连接得6678，jtag连接方式同上，我的在testconnection时卡在

[Start]

Execute the command:

%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -F inform,logfile=yes -S pathlength -S integrity

[Result]

—–[Print the board config pathname(s)]————————————

C:\DOCUME~1\ZHANGP~1\LOCALS~1\APPLIC~1\.TI\ 179728339\0\0\BrdDat\testBoard.dat

—–[Print the reset-command software log-file]—————————–

This utility has selected a 560/2xx-class product.This utility will load the program 'seed560v2u.out'.The library build date was 'May 30 2012'.The library build time was '23:17:26'.The library package version is '5.0.747.0'.The library component version is '35.34.40.0'.The controller does not use a programmable FPGA.The controller has a version number of '5' (0x00000005).The controller has an insertion length of '0' (0x00000000).The cable+pod has a version number of '8' (0x00000008).The cable+pod has a capability number of '7423' (0x00001cff).This utility will attempt to reset the controller.This utility has successfully reset the controller.

—–[Print the reset-command hardware log-file]—————————–

The scan-path will be reset by toggling the JTAG TRST signal.The controller is the Nano-TBC VHDL.The link is a 560-class second-generation-560 cable.The software is configured for Nano-TBC VHDL features.The controller will be software reset via its registers.The controller has a logic ONE on its EMU[0] input pin.The controller has a logic ONE on its EMU[1] input pin.The controller will use falling-edge timing on output pins.The controller cannot control the timing on input pins.The scan-path link-delay has been set to exactly '2' (0x0002).The utility logic has not previously detected a power-loss.The utility logic is not currently detecting a power-loss.

卡在这里运行不下去了，但是单独进每一片DSP都是可以的。请问是什么原因呢？jtag接口段通过sn74alvc244驱动。