TI中文支持网最近在做NOR flahs驱动，参考ICE板子代码，现在问题是，一往NORflash 地址空间进行读写时，就错误退出。不知是何原因。大神们帮忙看下，谢谢。
示波器测量信号时,并没有片选信号。
ARM:am3354
NORflash:s29GL01
配置代码：
//enable clock to GPMC module //----- 1、时钟使能HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL ) |= CM_PER_GPMC_CLKCTRL_MODULEMODE_ENABLE;//check to see if enabledwhile( (HWREG(SOC_PRCM_REGS + CM_PER_GPMC_CLKCTRL) & CM_PER_GPMC_CLKCTRL_IDLEST) != (CM_PER_GPMC_CLKCTRL_IDLEST_FUNC << CM_PER_GPMC_CLKCTRL_IDLEST_SHIFT));//reset the GPMC module//----- 2、复位GPMC模块HWREG(GPMC_BASE + GPMC_SYSCONFIG ) |= GPMC_SYSCONFIG_SOFTRESET;while((HWREG(GPMC_BASE + GPMC_SYSSTATUS) & GPMC_SYSSTATUS_RESETDONE) == GPMC_SYSSTATUS_RESETDONE_RSTONGOING); //Configure to no idle//----- 3、配置为no idle模式temp = HWREG(GPMC_BASE + GPMC_SYSCONFIG);temp &= ~GPMC_SYSCONFIG_IDLEMODE;temp |= GPMC_SYSCONFIG_IDLEMODE_NOIDLE << GPMC_SYSCONFIG_IDLEMODE_SHIFT;HWREG(GPMC_BASE + GPMC_SYSCONFIG) = temp;HWREG(GPMC_BASE + GPMC_IRQENABLE) = 0x0;HWREG(GPMC_BASE + GPMC_TIMEOUT_CONTROL) = 0x0;//configure for NOR and granularity x2//----- 4、配置参数,包括//-----位宽//-----wait pin选择//-----mux mode 选择HWREG(GPMC_BASE + GPMC_CONFIG1(csNum)) = (0x0 | (GPMC_CONFIG1_0_DEVICESIZE_SIXTEENBITS <<GPMC_CONFIG1_0_DEVICESIZE_SHIFT ) | (GPMC_CONFIG1_0_WAITPINSELECT_W1<<GPMC_CONFIG1_0_WAITPINSELECT_SHIFT)|(GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_SIXTEEN <<GPMC_CONFIG1_0_ATTACHEDDEVICEPAGELENGTH_SHIFT ));//----- ontime//----- de-assert-rd//----- de-assert-wrHWREG(GPMC_BASE + GPMC_CONFIG2(csNum)) = (0x0 |(CS_ON_TIME ) |(CS_DEASSERT_RD << GPMC_CONFIG2_0_CSRDOFFTIME_SHIFT) |(CS_DEASSERT_WR << GPMC_CONFIG2_0_CSWROFFTIME_SHIFT));//----- adv-assert//----- adv-assert-rd//----- adv-assert-wrHWREG(GPMC_BASE + GPMC_CONFIG3(csNum)) = (0x0 |(ADV_ASSERT << GPMC_CONFIG3_0_ADVONTIME_SHIFT) |(ADV_DEASSERT_RD << GPMC_CONFIG3_0_ADVRDOFFTIME_SHIFT) |(ADV_DEASSERT_WR << GPMC_CONFIG3_0_ADVWROFFTIME_SHIFT));//----- OE-ASSERT//----- OE-DE-ASSERT//----- WE-ASSERT//----- WE-DE-ASSERTHWREG(GPMC_BASE + GPMC_CONFIG4(csNum)) = (0x0 |(OE_ASSERT << GPMC_CONFIG4_0_OEONTIME_SHIFT) |(OE_DEASSERT << GPMC_CONFIG4_0_OEOFFTIME_SHIFT) |(WE_ASSERT << GPMC_CONFIG4_0_WEONTIME_SHIFT)|(WE_DEASSERT << GPMC_CONFIG4_0_WEOFFTIME_SHIFT));//----- RD-CYCLE//----- WR-CYCLE//----- RD-ACCESSHWREG(GPMC_BASE + GPMC_CONFIG5(csNum)) = (0x0 |(CFG_5_RD_CYCLE_TIM << GPMC_CONFIG5_0_RDCYCLETIME_SHIFT)|(CFG_5_WR_CYCLE_TIM << GPMC_CONFIG5_0_WRCYCLETIME_SHIFT)|(CFG_5_RD_ACCESS_TIM << GPMC_CONFIG5_0_RDACCESSTIME_SHIFT));//----- CYCLE2CYCLESAMECSEN//----- CYC2CYC_DELAY//----- WR_DATA_ON_ADMUX//----- WR_ACCESS_TIMHWREG(GPMC_BASE + GPMC_CONFIG6(csNum)) = (0x0 |(GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_C2CDELAY <<GPMC_CONFIG6_0_CYCLE2CYCLESAMECSEN_SHIFT) |(CYC2CYC_DELAY << GPMC_CONFIG6_0_CYCLE2CYCLEDELAY_SHIFT) |(WR_DATA_ON_ADMUX << GPMC_CONFIG6_0_WRDATAONADMUXBUS_SHIFT)|(CFG_6_WR_ACCESS_TIM << GPMC_CONFIG6_0_WRACCESSTIME_SHIFT));//----- BASE ADDR//----- CS VALID//-----HWREG(GPMC_BASE + GPMC_CONFIG7(0)) =(CFG_7_BASE_ADDR << GPMC_CONFIG7_0_BASEADDRESS_SHIFT) |(0x1 << GPMC_CONFIG7_0_CSVALID_SHIFT) |(CFG_7_MASK << GPMC_CONFIG7_0_MASKADDRESS_SHIFT);
其中
#define GPMC_BASE 0x50000000
#define FLASH_BASE ( 0x10000000)
Jian Zhou：
是用的starterware么？肯定是地址空间分配的问题。
Kevin_KDP：
回复 Jian Zhou:
感谢答复。
是用的starterware.我感觉也是地址空间分配的问题。
但是寄存器中关于地址空间分配的是不是主要是CONFIG7，我检查了几遍，未发现有问题。
config7中
MASKADDRESS bit[11-8] = 8h (采用128M norflash)
BASEADDRESS bit[5-0] = 0x00 (起始地址0x0000_0000)
读数据时
x = HWREG(FLASH_BASE);
一读取就错误退出。
Kevin_KDP：
回复 Jian Zhou:
将BASEADDRESS 改为 bit[5-0] = 0x10 (起始地址0x1000_0000)
#define FLASH_BASE 0x1000_0000时,
x = HWREG(FLASH_BASE);
读取数据同样错误退出.是不是还有其他问题呢？
Kevin_KDP：
回复 Jian Zhou:
@ Jian Zhou 还有其他建议吗？谢谢。
Kevin_KDP：
回复 Kevin_KDP:
附上config配置及原理图
Kevin_KDP：
回复 Kevin_KDP:
Kevin_KDP：
回复 Kevin_KDP:
问题确认，是因为接16位norflash时,地址线未左移一位导致。这样导致命令写入失败，从而不能进行后续操作。暂时将芯片配置为8位使用，后续改板解决。多谢各位。
Steven Liu1：
回复 Kevin_KDP:
建议硬件设计的时候先核查，我们TRM手册中的7.1.2.1 GPMC Signals章节中的Talbe 7-5 GPMC Pin Multiplexing Options表格，里面列出了所有的8bit和16bit NOR/NAND device的接线方式，这样可以避免掉这些硬件接线问题。
samuel han：
回复 Jian Zhou:
我们遇到了相同的问题，我们配置了NorFlash，原理图参考下图；试图读取地址0x8000000地址空间数据，同时测试测量CS0上的信号，发现该片选信号没有使能，持续为高电平，没有读取到任何数据，是否是我们的配置有问题，我们配置主要考虑了2个方面的内容：
1、 NorFlash对应的pin脚的配置；
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(1)) = /* NorFlash -> gpmc_ad1 -> V7 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_RXACTIVE |
CONTROL_CONF_GPMC_AD1_CONF_GPMC_AD1_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(2)) = /* NorFlash -> gpmc_ad2 -> R8 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_RXACTIVE |
CONTROL_CONF_GPMC_AD2_CONF_GPMC_AD2_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(3)) = /* NorFlash -> gpmc_ad3 -> T8 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_RXACTIVE |
CONTROL_CONF_GPMC_AD3_CONF_GPMC_AD3_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(4)) = /* NorFlash -> gpmc_ad4 -> U8 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_RXACTIVE |
CONTROL_CONF_GPMC_AD4_CONF_GPMC_AD4_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(5)) = /* NorFlash -> gpmc_ad5 -> V8 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_RXACTIVE |
CONTROL_CONF_GPMC_AD5_CONF_GPMC_AD5_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(6)) = /* NorFlash -> gpmc_ad6 -> R9 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_RXACTIVE |
CONTROL_CONF_GPMC_AD6_CONF_GPMC_AD6_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(7)) = /* NorFlash -> gpmc_ad7 -> T9 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_RXACTIVE |
CONTROL_CONF_GPMC_AD7_CONF_GPMC_AD7_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(8)) = /* NorFlash -> gpmc_ad8 -> U10 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_RXACTIVE |
CONTROL_CONF_GPMC_AD8_CONF_GPMC_AD8_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(9)) = /* NorFlash -> gpmc_ad9 -> T10 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_RXACTIVE |
CONTROL_CONF_GPMC_AD9_CONF_GPMC_AD9_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(10)) = /* NorFlash -> gpmc_ad10 -> T11 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_RXACTIVE |
CONTROL_CONF_GPMC_AD10_CONF_GPMC_AD10_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(11)) = /* NorFlash -> gpmc_ad11 -> U12 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_RXACTIVE |
CONTROL_CONF_GPMC_AD11_CONF_GPMC_AD11_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(12)) = /* NorFlash -> gpmc_ad12 -> T12 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_RXACTIVE |
CONTROL_CONF_GPMC_AD12_CONF_GPMC_AD12_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(13)) = /* NorFlash -> gpmc_ad13 -> R12 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_RXACTIVE |
CONTROL_CONF_GPMC_AD13_CONF_GPMC_AD13_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(14)) = /* NorFlash -> gpmc_ad14 -> V13 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_RXACTIVE |
CONTROL_CONF_GPMC_AD14_CONF_GPMC_AD14_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_AD(15)) = /* NorFlash -> gpmc_ad15 -> U13 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_RXACTIVE |
CONTROL_CONF_GPMC_AD15_CONF_GPMC_AD15_PUDEN) &
(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(1)) = /* NorFlash -> gpmc_a17 -> V14 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A1_CONF_GPMC_A1_PUDEN)));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(2)) = /* NorFlash -> gpmc_a18 -> U14 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A2_CONF_GPMC_A2_PUDEN)));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(3)) = /* NorFlash -> gpmc_a19 -> T14 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A3_CONF_GPMC_A3_PUDEN)));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(4)) = /* NorFlash -> gpmc_a20 -> R14 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A4_CONF_GPMC_A4_PUDEN)));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(5)) = /* NorFlash -> gpmc_a21 -> V15 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A5_CONF_GPMC_A5_PUDEN)));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(6)) = /* NorFlash -> gpmc_a22 -> U15 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A6_CONF_GPMC_A6_PUDEN)));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(7)) = /* NorFlash -> gpmc_a23 -> T15 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A7_CONF_GPMC_A7_PUDEN)));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(8)) = /* NorFlash -> gpmc_a24 -> V16 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A8_CONF_GPMC_A8_PUDEN)));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(9)) = /* NorFlash -> gpmc_a25 -> U16 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A9_CONF_GPMC_A9_PUDEN)));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(10)) = /* NorFlash -> gpmc_a26 -> T16 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A10_CONF_GPMC_A10_PUDEN)));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_A(11)) = /* NorFlash -> gpmc_a27 -> V17 */
PINMUXMODE_5 |
((0x38) &
((~CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_RXACTIVE)
&(~CONTROL_CONF_GPMC_AD_CONF_GPMC_AD_PUTYPESEL)
&(~CONTROL_CONF_GPMC_A11_CONF_GPMC_A11_PUDEN)));
/* control pins */
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_WEN ) = /* NorFlash -> gpmc_wen -> U6 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUDEN) &
(~CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_PUTYPESEL &
~CONTROL_CONF_GPMC_WEN_CONF_GPMC_WEN_RXACTIVE ));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_CSN(0) ) = /* NorFlash -> gpmc_csn0 -> V6 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUDEN) &
(~CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_PUTYPESEL &
~CONTROL_CONF_GPMC_CSN0_CONF_GPMC_CSN0_RXACTIVE ));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_OEN_REN) = /* NorFlash -> gpmc_oen_ren -> T7 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUDEN) &
(~CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_PUTYPESEL &
~CONTROL_CONF_GPMC_OEN_REN_CONF_GPMC_OEN_REN_RXACTIVE ));
HWREG(CTRL_MODULE_BASE_ADDR + CONTROL_CONF_GPMC_ADVN_ALE ) = /* NorFlash -> gpmc_advn_ale -> R7 */
PINMUXMODE_1 |
((CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUDEN) &
(~CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_PUTYPESEL &
~CONTROL_CONF_GPMC_ADVN_ALE_CONF_GPMC_ADVN_ALE_RXACTIVE ));
2、 CONFIG1~CONFIG7的配置；
config1 0x00001200
config2 0x001e1e00
config3 0x00030300
config4 0x1c0d1c05
config5 0x00181f1f
config6 0x0d070a80
config7 0x00000f48
其中下图锁存器芯片（74LVC16373）我们还用了一种sn74lvc16374
Steven Liu1：
回复 samuel han:
首先，建议使用374，沿锁存的器件。373至少在rom code boot这一级的验证中，是没法起来的。因为他是电平锁存，一定程度上影响到了时序。
还有建议下回直接发pinmux的寄存器读出来的值，不要发代码段，可读性太差。这里无非就是确认一个是当前的pin脚模式配置正确，一个是一些输出的管教和clk管教一定要配置成为receive enable。
再合一下，上面的这些是对的吗？
